During the circuit design process, application engineers often overlook the layout of the printed circuit board (PCB). The problem usually encountered is that the circuit is correctly schematised, but does not work or only operates at low performance. In this article, I will show you how to properly lay out an operational amplifier's board to ensure its functionality, performance, and robustness.

Recently, I was working with an intern on a design using a non-inverting configuration OPA191 operational amplifier with a gain of 2V/V, a load of 10kΩ, and a supply voltage of /-15V. The schematic of this design is shown in Figure 1. 

Figure 1: Schematic diagram of the OPA191 using a non-inverting configuration

I assigned an intern to lay out the board for the design, gave him general instructions on PCB layout (i.e., shorten the board's route as much as possible while keeping components close together to reduce board space), and then left him to design it on his own. How difficult was the design process? It's just a few resistors and capacitors, isn't it?

Figure 2 shows the layout of his first attempt. The red lines show the paths on the top layer of the board, while the blue lines show the paths on the bottom layer.

Figure 2: First Layout Attempt Solution Seeing his first layout attempt, I realised that the board layout was not as intuitive as I had thought; I should have at least given him some more detailed instructions. He followed my advice to the letter: he shortened the routing paths and placed the components close together. But there was still a lot of room for improvement to reduce the board's parasitic impedance and optimise its performance.

The next step was to improve the layout. The first improvement we made was to move resistors R1 and R2 next to the inverting pin (pin 2) of the OPA191; this helps to reduce the stray capacitance of the inverting pin. The op-amp's inverting pin is a high-impedance node and therefore has a higher sensitivity. The longer alignment path serves as a wire to allow high frequency noise to couple into the signal chain. PCB capacitance on the inverting pin can cause stability problems. Therefore, the contact on the inverting pin should be as small as possible.

Moving R1 and R2 next to pin 2 allows the load resistor R3 to be rotated 180 degrees, thus bringing the decoupling capacitor C1 closer to the positive power pin (pin 7) of the OPA191. It is extremely important to keep the decoupling capacitor as close to the power supply pin as possible. A long alignment path between the decoupling capacitor and the power supply pin will increase the inductance of the power supply pin, which will degrade performance.

Another improvement we made was in the second decoupling capacitor, C2. Instead of placing the lead hole connection from VCC to C2 between the capacitor and the power supply pin, it should be routed where the supply voltage has to pass through the capacitor into the power supply pin of the device. Figure 3 shows how the layout can be improved by moving each component and the vias.

Figure 3: Improving the location of the components of the layout After moving the components to their new locations, there are still some other improvements that can be made. You can widen the alignment path to reduce the inductance, which is equivalent to the size of the pads to which the alignment path connects. You can also perf the ground layers at the top and bottom of the board to create a solid, low-impedance path for the return current. Our final layout is shown in Figure 4.

Figure 4: Final Layout Next time you lay out a printed circuit board, it is recommended that you follow the following layout conventions:

● Keep the inverting pin connections as short as possible.

● Place decoupling capacitors as close as possible to the power supply pins.

● If multiple decoupling capacitors are used, place the smallest decoupling capacitor closest to the power supply pin.

● Do not place a pilot hole between the decoupling capacitor and the power supply pin.

● Widen the alignment path as much as possible.

● Do not allow 90-degree angles in the alignment path.

● Perfuse at least one solid ground layer.

● Do not discard a good layout in order to mark parts with a silkscreen layer.

Above, we talked about the proper way to layout an instrumentation amplifier (op amp) PCB and provided a series of good layout practices to follow. Next, common mistakes made when laying out an instrumentation amplifier (INA) will be explored, and then the INA PCB will be shown to be laid out correctly.

INAs are used in applications that require amplification of differential voltages, such as measuring the voltage through a shunt resistor in a high-side current-sense application. A schematic diagram of a typical single-supply high-side current-sense circuit is shown in Figure 5.

Figure 5: High Side Current Sense Schematic Figure 5 measures the differential voltage through the RSHUNT, R1, R2, C1, C2 and C3 are used to provide common mode and differential mode filtering, R3 and C4 provide the output filtering of the U1 INA, and U2 is used to buffer the INA's reference pins.R4 and C5 are used to form a low-pass filter to minimise the noise that the op-amp introduces to the INA's reference pins.

Although the schematic layout in Figure 5 looks intuitive, it is very easy to make mistakes in the PCB layout, resulting in degraded circuit performance. Figure 6 shows three common errors made by staff when checking the INA layout.

Figure 6: INA Common PCB Layout As seen in the above figure, the first error is the way the differential voltage Rshunt through the resistor is measured. It can be seen that the line from Rshunt to R2 is shorter and therefore its resistance is less than the resistance of the line from Rshunt to R1. This difference in line impedance may introduce an input bias current to the INA causing a differential voltage on the U1 input side. Since the task of the INA is to amplify the differential voltage, an unbalanced line on the input side may result in an error. Therefore, it is necessary to ensure that the INA input lines are balanced and as short as possible.

The second error is related to the INA gain setting resistor Rgain. the line from the U1 pin to the Rgain pad is longer than the actual required length, resulting in extra resistance and capacitance. Since the gain depends on the resistance between the INA gain setting pins, pin 1 and pin 8, the extra resistance may give the wrong target gain. And since the gain setting pin of the INA is connected to the feedback section within the INA, the extra capacitance may cause stability problems. Therefore, it needs to be ensured that the line connecting the gain setting resistor should be as short as possible.

Finally, the location of the reference pin of the buffer circuit may need to be improved. Reference pin buffer circuits are located further away from the reference pin, which may increase the resistance connecting to the reference pin, resulting in noise or other signals that may be coupled into the line. The additional resistance on the reference pin may reduce the high common mode rejection ratio (CMRR) provided by most INAs. Therefore, the reference pin buffer circuit needs to be arranged as close as possible to the INA reference pin.

The layout after correcting these three types of errors is shown in Figure 7.

Figure 7: PCB Layout After Correcting Three Types of Errors In Figure 7, it can be seen that the lines from R1 and R2 to the shunt resistor are the same length and use a Kelvin connection. The line from the gain setting resistor to the INA pin was made as short as possible, and the reference buffer circuit was placed as close to the reference pin as possible.

If you are laying out a PCB for the INA in the future, be sure to follow these principles:

● Ensure that all lines on the input side are completely balanced;

● Reduce line lengths and minimise capacitance on the gain setting pins;

● Arrange the reference buffer circuit as close as possible to the INA reference pins;

● Locate the reference buffer circuit as close as possible to the INA reference pin;

● Locate the decoupling capacitors as close as possible to the power supply pins;

● Overlay at least one solid ground plane;

● Do not sacrifice good layout to use silkscreen for components;

● Follow the guidelines mentioned in the first part of this article.

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