Circuit timing is a critical function required in a wide range of electronic devices, including microcontrollers, USB, Ethernet, Wi-Fi, and Bluetooth interfaces, as well as computing devices and peripherals, medical devices, test and measurement equipment, industrial control and automation, the Internet of Things (IoT), wearables, and consumer electronics. Providing system timing by designing a crystal-controlled oscillator may seem simple at first, but there are many parameters and design requirements that designers must consider when matching a quartz crystal to an oscillator IC.

There are many factors to consider, including crystal motion impedance, resonance mode, excitation power, and negative oscillator resistance. In terms of circuit layout, the designer needs to consider the parasitic capacitance of the PC board, the inclusion of a protective band around the crystal, and on-chip integrated capacitors. The final design needs to be compact and reliable, with a minimum number of components, low root-mean-square (rms) jitter, and minimal power consumption over a wide input voltage range.

Siple Packaged Crystal Oscillators (SPXOs) are the solution. These continuous voltage oscillators are optimised for low power consumption and low RMS jitter and can operate at any voltage between 1.60 V and 3.60 V, allowing designers to achieve a solution that can be integrated into a system with minimal design effort.

This paer will briefly discuss some of the important performance requirements that must be met and design challenges that must be overcome to successfully design timing circuits using discrete quartz crystals and timing ICs. Abracon's SPXO solutions will then be introduced to show how designers can use these devices to effectively and efficiently meet the timing needs of electronic systems.

Crystal Oscillator Operation and Design Challenges

Power consumption is an important consideration for small battery-powered wireless devices. Many similar devices are based on very low-power system-on-chip (SoC) radios and processors that can support years of continuous battery life. In addition, since the battery is probably the most expensive component in the system, minimising its size is important to keep device costs in check. That said, standby current is often the most important battery life consideration in small wireless systems, and standby current is often dominated by the clock oscillator. Therefore, it is critically good to minimise the current consumption of the oscillator.

Unfortunately, designing low-power oscillators can be challenging. One way to save energy is to minimise standby current by entering a ‘disabled’ state and starting the oscillator when needed. However, requiring a crystal oscillator to start up quickly and reliably is not easy. Designers need to ensure that the oscillator is in a low-current state in standby and has reliable start-up characteristics under all operating and environmental conditions.

The Pierce oscillator configuration is commonly found in low-power wireless SoCs (Figure 1).The Pierce oscillator is built based on a crystal (X) and load capacitors (C1 and C2) and is surrounded by an inverting amplifier that uses internal feedback resistors. Under the right conditions, when the output of the amplifier is fed back to the input, a negative resistance is created and oscillation occurs.

Figure 1: Basic Pierce oscillator configuration built around a crystal (X) and load capacitors C1 and C2. (Photo credit: Abracon)

Crystal structures are complex; this discussion is only about the top-level and simplified structure of a crystal operating in an oscillator.

Closed-loop gain margin Gm can be used as a quality factor (FOM) to describe the reliability of an oscillator with respect to various losses. Closed loop gain margin is also referred to as oscillation allowance (OA). an OA below 5 results in low production throughput and temperature related startup issues. designs with an OA equal to or greater than 20 are robust, operate reliably over the design operating temperature range, and have minimal impact on crystal and SoC performance characteristics from production lot to production lot.

To measure the OA of an oscillator, add a variable resistor, Ra, to the circuit (Figure 2). Increase the Ra value until the oscillator fails to start. This is used to determine the OA value as follows:

OA = Rn/Re

Equation 1 

where:

Rn is the negative resistance

Re is the equivalent series resistance (ESR).

Equation 2

Equation 3

Where the load capacitance CL is calculated as follows:

Equation 14

where Cs is a variable capacitor for the circuit, with capacitance values typically ranging from 3.0 to 5.0 pF.

Figure 2: Shows the extended crystal model (middle box) and the adjustable resistor (Ra) used to measure the oscillation margin. (Photo credit: Abracon)

OA depends on ESR (Re), which in turn depends on the quartz crystal parameter Rm and the load capacitance CL. For low-power oscillators, such as those used in low-power wireless devices, the effect of Rm and CL on OA increases. Measuring OA is time-consuming and may prolong the development process. As a result, this task may be overlooked, leading to performance problems when the system or device is put into production.

In addition, ensuring reliable oscillator operation by setting OA high can lead to other problems. For example, the higher the OA, the higher the performance of the oscillator circuit, but the power loss due to the crystal may be ignored. This loss can be a significant factor. Turning to Figure 2, the crystal movement resistor, Rm, causes power dissipation as current flows periodically through the resistor. When CL is large, it increases the current and losses. Therefore, the designer needs to strike a balance between the power loss of the crystal and a reasonable OA value.

Avoiding Jitter

When designing a quartz crystal oscillator, it is important to understand and reduce jitter. There are two types of jitter, both of which are usually measured as root-mean-square (RMS) values:

Inter-cycle jitter: Also called phase jitter, this is the maximum time difference between several measured oscillation cycles, usually measured over a minimum of 10 cycles.

Cyclic Jitter: This is the maximum variation along a clock edge and is measured for each cycle, not multiple cycles.

Major sources of jitter in quartz crystal oscillators include power supply noise, integer harmonics of the signal frequency, improper load and termination conditions, amplifier noise, and certain circuit configurations. Depending on the source, different methods can be used to minimise jitter.

Use bypass capacitors, chip beads, or resistive capacitor (RC) filters to control power supply noise.

In critical applications where very low jitter is required, it is critical to establish a method of controlling harmonics (which is beyond the scope of this paper).

Reduce the amount of power reflected back to the output by optimising load and termination conditions.

Avoid designs that include phase-locked loops, multipliers, or programmable functions, as they tend to increase jitter.

Continuous Voltage Crystal Oscillators

The use of Abracon's ASADV, ASDDV, and ASEDV SPXOs facilitates the design of systems with bias voltages varying from 1.60 to 3.60 V (Figure 3). The SPXO series covers a variety of frequency ranges; the ASADV devices are available from 1.25 MHz to 100 MHz, and the ASDDV and ASEDV devices are available from 1 MHz to 160 MHz. They are RoHS/RoHS II compliant and are available in hermetically sealed ceramic surface mount device (SMD) packages. The series has a frequency stability of ±25ppm over the -40°C to +85°C operating temperature range.

Figure 3: The ASADV (shown), ASDDV, and ASEDV SPXOs are available in hermetically sealed ceramic packages with operating temperatures ranging from -40°C to +85°C. (Photo credit: Abracon)

The ASADV measures 2.0 x 1.6 x 0.8 mm, the ASDDV measures 2.5 x 2.0 x 0.95 mm, and the ASEDV measures 3.2 x 2.5 x 1.2 mm. The three families operate over a wide range of common operating temperatures, offer a variety of stability options, and are available in CMOS/HCMOS/LVCMOS compatible output formats.

Importantly, the ASADV, ASDVD, and ASEDV series are optimised for low current operation (Figure 4). The output enable/disable feature reduces the current to only 10 μA when disabled, and these devices have a maximum start-up time of 10 ms.

Figure 4: ASEDV current consumption versus supply voltage, which is typical of the performance of this SPXO family of devices (measured at 25°C ± 3°C). (Image credit: Abracon)

All three families of SPXOs have exceptionally low current consumption. For ASADV, the maximum current range is from 1.0 mA at 1.25 MHz and 1.8 V supply voltage to 14.5 mA at 81 MHz and 3.3 V supply voltage when measured at 25°C with a 15 pF load, and for ASDDV and ASEDV, the maximum current range is from 1.0 mA at 1 MHz and 1.8 V supply voltage to 157 MHz and 3.3 V supply voltage. For ASDDV and ASEDV, the maximum current ranges from 1.0 mA at 1 MHz and 1.8 V supply voltage to 19 mA at 157 MHz and 3.3 V supply voltage.

These devices can drive multiple loads and offer good electromagnetic interference (EMI) performance and low jitter. The devices have root-mean-square phase jitter of <1.0 ps and maximum cycle jitter of 7.0 ps.

The SPXOs also have good frequency stability over the full operating temperature range (Figure 5). In many applications, these oscillators can be used as a plug-and-play solution with no design effort required. With these oscillators, there is no need to select a bias-specific oscillator and bias-related frequency variations are eliminated.

Figure 5: These SPXOs have good frequency stability over the entire operating temperature range. This figure is typical of the ASEDV series. (Photo credit: Abracon)

Finally, the ASADV, ASDVD, and ASEDV continuous voltage surface mount crystal oscillators can be used as a low-cost alternative to microelectromechanical systems (MEMS) oscillators when shock and vibration are not critical considerations.

Summary

Designers need accurate and reliable oscillators that provide stable timing over a wide range of applications and operating temperatures. Discrete crystal-controlled oscillators can meet the required performance characteristics, but are technically difficult to design efficiently with crystals and are time consuming and unnecessarily costly. In addition, it is not optimal in terms of form factor.

As shown in the figure, designers can use low-power integrated SPXOs, which form a ready-to-use timing solution with excellent frequency stability over a wide operating temperature range. Using SPXOs, designers can reduce component count, shrink solution size, lower assembly costs and increase reliability.

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