# Step-by-Step Procedure for Calculating DC-DC Compensation Networks

By Rani Feldman, Field Applications Engineer

**Summary**

This article is intended to help designers understand how DC-DC compensation works, the necessity of a compensation network, and how to easily obtain effective results using the right tools. The method uses a simple circuit in LTspice® based on a first-order (linear) model of a current-mode buck converter1. Using this circuit, compensation network values can be verified without performing complex mathematical calculations.

background knowledge

When designing a DC-DC converter, components such as FETs, inductors, current sense resistors, and output capacitors should be carefully selected to match the required output voltage ripple and transient performance. After designing the power stage, it is also important to close the loop. The DC-DC power supply contains a negative feedback loop using an error amplifier (EA). A signal propagating in a negative feedback system may encounter poles and zeros along its path. A single pole reduces the phase of the signal by approximately 90° and reduces the gain slope by -20 dB/Dec, while a single zero increases the phase by approximately 90° and increases the gain by +20 dB/Dec. If the phase of the signal is reduced by -180°, the negative feedback loop may become a positive feedback loop and oscillate. Keeping the loop stable and avoiding oscillations are design guidelines for power supplies.

There are two ways to test DC-DC stability. The first is Frequency Response Analysis (FRA), which creates a Bode plot. The second method is time domain analysis, which will cause a transient in the load current and observe the undershoot and overshoot response of the output voltage. For a stable design, be sure to avoid phase drops of -180° and keep the phase margin (PM) greater than 45°. A phase margin of 60° is ideal. When the bandwidth (BW) of the power supply design is wider, the device responds faster to changes in current load. The bandwidth of a power supply is the frequency at which 0 dB gain intersects the frequency axis. This frequency is also called the crossover frequency Fc and can be observed to have a phase higher than 45°. The bandwidth of a DC-DC converter is the derivative of its switching frequency Fsw, usually in the range of Fsw/10 < Fc < Fsw/5. The closer it is to Fsw/5, the wider the bandwidth, and it will be more difficult to implement. The wider the bandwidth, the lower the phase, so there are design tradeoffs. Gain margin (GM) is the negative gain at Fsw/2 and –180°, a value of -8 dB or higher will provide good attenuation of possible switching noise, or reduced gain at -180° phase shift possibility. We want to cross the 0 dB point with a slope of -20 dB/Dec.

Figure 1. Bode plot showing bandwidth, phase, gain margin, and crossover frequency Fc at 0 dB.

Figure 2. The wider the power supply bandwidth, the faster the device responds to changes in current load.

Power stage LC filter

Power stage LC filter refers to the inductor and equivalent output capacitance of a given topology (buck, boost, etc.). There are two commonly used architectures for various topologies: voltage mode (VM) and current mode (CM). The same LC filter in VM architecture and CM architecture will produce different behaviors. Simply put, the LC filter used in the VM architecture adds two poles. The CM architecture additionally includes a current sense feedback path that helps eliminate the double poles of the LC filter. The VM architecture is difficult to compensate because the LC double pole requires more zeros to offset the double pole effect, thus requiring more components.

Buck VM architecture and LC frequency behavior

The LC filter will result in the addition of two poles and a zero due to the equivalent output capacitance CEQ and its equivalent ESR (ESREQ):

The position of the LC filter double pole has nothing to do with the LC parasitic resistance. The larger the inductance and equivalent capacitance values are, the closer the double pole position will be to the origin of the frequency axis, 0 Hz. If the CEQ and its ESREQ values are higher, the LC filter zero frequency location will move to the left or closer to 0 Hz. The behavior of the LC filter in VM is shown in Figure 3, and its simulation results are shown in Figure 4. The difference between the red and blue lines is due to the capacitor ESR values, which are 1 mΩ and 100 mΩ respectively. The Fr position is the same because the LC value does not change, but the zero position changes due to the change in the ESR value.

Figure 3. Simplified model circuit of VM step-down LC filter behavior

For the VM architecture, the LC filter adds two poles and a zero. The frequency response shape is always the same: the slope changes from 0 dB/Dec to -40 dB/Dec to -20 dB/Dec. The location of the poles and zeros depends on the inductor, total capacitance, and equivalent capacitance ESR values.

Figure 4. Simulation results of simplified VM buck LC filter behavior

CM architecture and LC frequency behavior

The frequency behavior of the LC filter in CM can be simulated by a voltage-controlled current source, as shown in Figure 5. The ESR steps between two values to highlight the difference in zero position. The pole position of the LC filter in the CM buck architecture is calculated from the following equation:

RLOAD is the load resistance, which is the ratio of output voltage to current. For example, if the output voltage is 5 V and the load current is 2 A, RLOAD will be equal to 5 V/2 A = 2.5 Ω. The zero point position is determined by the equivalent output capacitance and its equivalent ESR. Similar to the VM architecture, the two zero-point values corresponding to 1 mΩ and 100 mΩ ESR are:

Figure 5. Model of voltage-controlled current source used as CM buck; ESR is stepping

For the CM architecture, the LC filter adds a pole and a zero. The frequency response shape is always the same: the slope changes from 0 dB/Dec to -20 dB/Dec to 0 dB/Dec. The frequency location of the pole/zero depends on the output capacitance, equivalent ESR and load value.

Compensator

LC filters cause phase loss. The compensation network is used to compensate for the phase, by adding poles and zeros to the loop, which cancels out the phase lag/lead and gain changes caused by the LC filter.

Figure 6. Simulation of frequency response shape of CM buck LC filter

Current mode architecture compensator

The CM architecture compensator is called type 2 compensator. Figure 7 shows a Type 2 compensator. AD8038 is EA, R2 and R3 are feedback resistors, R4 is a resistor, and V1 injects frequency into the loop through R4 to perform FRA. The compensation network consists of R1, C1 and C2.

Figure 7. Type 2 compensator model in LTspice

Expected results for zeros/poles and gains:

Gain(bzp) is the gain between zero and pole, determined by the ratio of R1 and R3. Gain(rz) is DC gain. In the calculation above, a frequency of 1 Hz is used for the pole at the origin; therefore, the initial slope of the compensator is -20 dB/Dec. Figure 8 shows that the simulation results are closely related to the calculated values.

Figure 8. Type 2 compensator simulation results, pole/zero positions and slope changes

VM architecture compensator

In the VM architecture, the compensator has an additional pole/zero combination that offsets the additional phase loss of the LC filter. Figure 9 shows the type 3 compensator network used in the VM architecture and Figure 10 shows its frequency response.

Figure 9. VM architecture compensator, also known as Type 3 compensator

C3 and R5 are two additional components in parallel with the top feedback resistor R3. The pole and zero positions of type 3 compensator are:

Please note that Fz1(EA) and Fz2 are placed at the same frequency. Sometimes a compensation scheme like Type 3 is used, where a single capacitor is designed on the top feedback resistor to remove the high frequency pole, and the compensator slope will continue to remain at 0 dB.

Figure 10. LTspice AC simulation results of VM compensator circuit

Adjust the time constant to be consistent

One way to close the loop is to have the LC filter pole/zero time constant coincide with the compensator zero/pole time constant, which cancels each other out and provides a total gain slope of -20 dB/Dec.

Figure 11. Adjustment to align the poles and zeros of the LC filter and compensator in VM and CM

Figure 12. LTC3981 28 V to 5 V/6 A design schematic with misaligned compensation network

Figure 13. Compensation network is misaligned, switching frequency is different from design frequency, transient test causes oscillation

Align poles/zeroes using a first-order average model

The LTC3891 is a CM controller designed to step down 28 V to 5 V/6 A. The compensation network on the ITH pin is inconsistent with the equivalent output capacitance and its total ESR, causing oscillation during transient load testing. The switching frequency measured at the output is 23 kHz instead of the expected 500 kHz.

The two circuits of power stage and compensator are combined to form a linear circuit that simulates the closed-loop behavior of the CM architecture.

Figure 14. Linear circuit emulating a CM regulator with misaligned compensation network

Figure 15. Simulation results of linear model, using amplifier as error amplifier, constants are inconsistent

G1 is a voltage controlled current source. Its value is 6, which means that if the voltage at the positive input of G1 is 1 V, its output will provide 6 A. The frequency response of this circuit shows different slope changes at different rates, with a phase of 25° at the 0 dB crossover frequency. Therefore, there are oscillations in the time domain.

To make the time constants consistent, we first need to know the CEQ, ESREQ and RLOAD of the power stage.

R1 is chosen by the designer; here R1 = 11.5 kΩ is chosen, the same as R3. R1 × C1(z) = CEQ × RLOAD(p). Solve for C1:

Figure 16. After pole/zero adjustment alignment, using amplifier as linear model of EA

CEQ × ESREQ (Z) = R1 × C3 (P), the time constant of the compensator pole is determined by R1 × C3. Solve for C3:

When using this average model, the correct simulation results show a slope of -20 dB/Dec and a phase of 90°. If the results are different, you need to verify the calculation.

One of the disadvantages of using an op amp as an EA is that the bandwidth cannot be predicted correctly. Nonetheless, this method is still very practical and can help verify consistent calculations. The bandwidth can be increased by increasing the R1 resistor value. If R1 increases, the compensator capacitance needs to decrease in the same proportion to keep the time constant consistent. R1 cannot be increased indefinitely because the higher the gain, the lower the phase margin at 0 dB. When the time constants are consistent, the phase will always remain 90°. The calculated values need to be verified using the IC switch model, and then transient response benchmarks need to be performed.

Figure 17. Results after pole/zero adjustment alignment, slope of -20 dB/Dec, high phase value of 90°

Figure 18. Compensation network on ITH pin aligned with output LC filter

Figure 19. Simulation results obtained by keeping the relevant values of the compensation network and LC filter consistent, showing a stable response to load transients.

Replacing the op amp with another voltage-controlled current source simplifies the linear model and improves its accuracy. The LTC3891 data sheet provides transconductance values, gm = 2 mmho at 1.2 V. The G1 positive input is 1 V, so the new current value will be 7.2, since 7.2 A/1.2 V = 6 A/V. A simulation of the new circuit (Figure 20) is shown in Figure 21 and the predicted bandwidth will be 46 kHz.

Figure 20. A simpler alignment circuit using G2 as the error amplifier. Its corresponding gm value is taken from the data sheet.

LTpowerCAD predicts a bandwidth of 57 kHz and a phase margin of 52°. The gain plots look very similar. The phase is very close at first but cannot be predicted correctly after 10 kHz.

Right half plane zero (RHPZ)

The RHPZ zero adds 20 dB of gain and reduces the phase by approximately 90°, making it impossible to compensate. For topologies such as boost, buck-boost, and sepic operating in continuous conduction mode, this zero will limit the bandwidth. The frequency position of RHPZ is calculated as follows:

Figure 21. A simpler circuit model using G2 as EA provides wider bandwidth

Figure 22. LTpowerCAD results for the LTC3891 design in Figure 18

Typically, in these equations, "inductance" is the only variable that requires trade-offs by the designer. The RHPZ location limits the bandwidth of the design because the loop needs to close at a frequency of F(RHPZ)/10. The linear model circuit presented here does not take RHPZ into account.

Voltage Mode Buck-Boost Example

The LTC3533 is a VM architecture buck-boost regulator. In boost mode, its RHPZ will be the limiting factor. The LTC3533 demo board is configured for 3.3 V/1.5 A when the input is VIN(MIN) of 2.4 V. In this case, the duty cycle D will be D = (Vo – VIN)/ Vo = (3.3 – 2.4)/3.3 ≈ 0.27. RLOAD = VOUT/IOUT = 3.3/1.5 = 2.2 Ω.

The RHPZ position can be found by any of the following formulas:

The safe position for a closed loop would be at 8.4 kHz. Rt sets the switching frequency Fsw = 1 MHz. Note that due to the lack of RFF, this compensation is type 3-like, so Cff does not create additional high frequency poles.

The positions of the poles and zeros are:

fP[CFF/RFF] → not used (31)

The double pole position of the LC filter is at 15.65 kHz. The two zeros Fz1 and FzCff are clustered together at about 9 kHz to cancel the poles of the LC filter. Additionally, the effect of the zero created by the LC filter at 967 kHz is canceled by the pole at 896 kHz.

Figure 23. LTC3533 demonstration board schematic

Figure 24. First-order model of EA’s VM architecture using op amps; LTC3533 demo board values

Figure 25. Simpler circuit for VM control using a voltage-controlled voltage source

Figure 26. Simulation results of two circuits

An average LTspice circuit using an op amp as EA's VM architecture can be used to check the alignment of poles and zeros. The circuit can be further simplified by using a voltage-controlled voltage source as the EA. Its gain value is derived from the error amplifier AVOL specified in the data sheet, which is 80 dB. 80dB = 20log10000. Therefore, 10000 was used in the simulation. Simulation of both circuits provides very similar solutions. The bandwidth does not vary as in CM circuit simulation. Gains are very similar and phase predictions are 90°, but that just goes to show that correct alignment is possible. The output has an additional 188 μF capacitor and a 0.2 Ω resistor. As shown in Figure 4, voltage-mode LC filters can produce high Q, especially when the values of ESR and DCR are low. To ensure that the LC filter has appropriate damping, an additional RC needs to be added to the output. The specific calculation is as follows:

**Conclusion**

LTspice circuit simulation provides an efficient and reliable method for verifying the calculation of the compensation network. Although the linear model discussed does not include current sensing components, signal gain or RHPZ information, designers will benefit from the fast simulation speed and compatibility with various DC-DC topologies. Furthermore, if the results obtained are correct, the output will show a gain slope of -20 dB/Dec and a phase of approximately 90°.

**References**

1.Henry J. Zhang. “Modeling and Loop Compensation Design for Switch-Mode Power Supplies.” Analog Devices, January 2015.

2. "LTspice Simulation Files for Power Stages and Average Compensation Models." Analog Devices, Inc.

“LTspice simulation files for power stage and average compensation models.” Analog Devices.

First-order (linear) model of a buck converter1. Using this circuit, compensation network values can be verified without performing complex mathematical calculations.

**Background**

When designing a DC-DC converter, components such as FETs, inductors, current sense resistors, and output capacitors should be carefully selected to match the required output voltage ripple and transient performance. After designing the power stage, it is also important to close the loop. The DC-DC power supply contains a negative feedback loop using an error amplifier (EA). A signal propagating in a negative feedback system may encounter poles and zeros along its path. A single pole reduces the phase of the signal by approximately 90° and reduces the gain slope by -20 dB/Dec, while a single zero increases the phase by approximately 90° and increases the gain by +20 dB/Dec. If the phase of the signal is reduced by -180°, the negative feedback loop may become a positive feedback loop and oscillate. Keeping the loop stable and avoiding oscillations are design guidelines for power supplies.

There are two ways to test DC-DC stability. The first is Frequency Response Analysis (FRA), which creates a Bode plot. The second method is time domain analysis, which will cause a transient in the load current and observe the undershoot and overshoot response of the output voltage. For a stable design, be sure to avoid phase drops of -180° and keep the phase margin (PM) greater than 45°. A phase margin of 60° is ideal. When the bandwidth (BW) of the power supply design is wider, the device responds faster to changes in current load. The bandwidth of a power supply is the frequency at which 0 dB gain intersects the frequency axis. This frequency is also called the crossover frequency Fc and can be observed to have a phase higher than 45°. The bandwidth of a DC-DC converter is the derivative of its switching frequency Fsw, usually in the range of Fsw/10 < Fc < Fsw/5. The closer it is to Fsw/5, the wider the bandwidth, and it will be more difficult to implement. The wider the bandwidth, the lower the phase, so there are design tradeoffs. Gain margin (GM) is the negative gain at Fsw/2 and –180°, a value of -8 dB or higher will provide good attenuation of possible switching noise, or reduced gain at -180° phase shift possibility. We want to cross the 0 dB point with a slope of -20 dB/Dec.

Figure 1. Bode plot showing bandwidth, phase, gain margin, and crossover frequency Fc at 0 dB.

Figure 2. The wider the power supply bandwidth, the faster the device responds to changes in current load.

Power stage LC filter

Power stage LC filter refers to the inductor and equivalent output capacitance of a given topology (buck, boost, etc.). There are two commonly used architectures for various topologies: voltage mode (VM) and current mode (CM). The same LC filter in VM architecture and CM architecture will produce different behaviors. Simply put, the LC filter used in the VM architecture adds two poles. The CM architecture additionally includes a current sense feedback path that helps eliminate the double poles of the LC filter. The VM architecture is difficult to compensate because the LC double pole requires more zeros to offset the double pole effect, thus requiring more components.

Buck VM architecture and LC frequency behavior

The LC filter will result in the addition of two poles and a zero due to the equivalent output capacitance CEQ and its equivalent ESR (ESREQ):

The position of the LC filter double pole has nothing to do with the LC parasitic resistance. The larger the inductance and equivalent capacitance values are, the closer the double pole position will be to the origin of the frequency axis, 0 Hz. If the CEQ and its ESREQ values are higher, the LC filter zero frequency location will move to the left or closer to 0 Hz. The behavior of the LC filter in VM is shown in Figure 3, and its simulation results are shown in Figure 4. The difference between the red and blue lines is due to the capacitor ESR values, which are 1 mΩ and 100 mΩ respectively. The Fr position is the same because the LC value does not change, but the zero position changes due to the change in the ESR value.

Figure 3. Simplified model circuit of VM step-down LC filter behavior

For the VM architecture, the LC filter adds two poles and a zero. The frequency response shape is always the same: the slope changes from 0 dB/Dec to -40 dB/Dec to -20 dB/Dec. The location of the poles and zeros depends on the inductor, total capacitance, and equivalent capacitance ESR values.

Figure 4. Simulation results of simplified VM buck LC filter behavior

CM architecture and LC frequency behavior

The frequency behavior of the LC filter in CM can be simulated by a voltage-controlled current source, as shown in Figure 5. The ESR steps between two values to highlight the difference in zero position. The pole position of the LC filter in the CM buck architecture is calculated from the following equation:

RLOAD is the load resistance, which is the ratio of output voltage to current. For example, if the output voltage is 5 V and the load current is 2 A, RLOAD will be equal to 5 V/2 A = 2.5 Ω. The zero point position is determined by the equivalent output capacitance and its equivalent ESR. Similar to the VM architecture, the two zero-point values corresponding to 1 mΩ and 100 mΩ ESR are:

Figure 5. Model of voltage-controlled current source used as CM buck; ESR is stepping

For the CM architecture, the LC filter adds a pole and a zero. The frequency response shape is always the same: the slope changes from 0 dB/Dec to -20 dB/Dec to 0 dB/Dec. The frequency location of the pole/zero depends on the output capacitance, equivalent ESR and load value.

Compensator

LC filters cause phase loss. The compensation network is used to compensate for the phase, by adding poles and zeros to the loop, which cancels out the phase lag/lead and gain changes caused by the LC filter.

Figure 6. Simulation of frequency response shape of CM buck LC filter

Current mode architecture compensator

The CM architecture compensator is called type 2 compensator. Figure 7 shows a Type 2 compensator. AD8038 is EA, R2 and R3 are feedback resistors, R4 is a resistor, and V1 injects frequency into the loop through R4 to perform FRA. The compensation network consists of R1, C1 and C2.

Figure 7. Type 2 compensator model in LTspice

Expected results for zeros/poles and gains:

Gain(bzp) is the gain between zero and pole, determined by the ratio of R1 and R3. Gain(rz) is DC gain. In the calculation above, a frequency of 1 Hz is used for the pole at the origin; therefore, the initial slope of the compensator is -20 dB/Dec. Figure 8 shows that the simulation results are closely related to the calculated values.

Figure 8. Type 2 compensator simulation results, pole/zero positions and slope changes

VM architecture compensator

In the VM architecture, the compensator has an additional pole/zero combination that offsets the additional phase loss of the LC filter. Figure 9 shows the type 3 compensator network used in the VM architecture and Figure 10 shows its frequency response.

Figure 9. VM architecture compensator, also known as Type 3 compensator

C3 and R5 are two additional components in parallel with the top feedback resistor R3. The pole and zero positions of type 3 compensator are:

Please note that Fz1(EA) and Fz2 are placed at the same frequency. Sometimes a compensation scheme like Type 3 is used, where a single capacitor is designed on the top feedback resistor to remove the high frequency pole, and the compensator slope will continue to remain at 0 dB.

Figure 10. LTspice AC simulation results of VM compensator circuit

Adjust the time constant to be consistent

One way to close the loop is to have the LC filter pole/zero time constant coincide with the compensator zero/pole time constant, which cancels each other out and provides a total gain slope of -20 dB/Dec.

Figure 11. Adjustment to align the poles and zeros of the LC filter and compensator in VM and CM

Figure 12. LTC3981 28 V to 5 V/6 A design schematic with misaligned compensation network

Figure 13. Compensation network is misaligned, switching frequency is different from design frequency, transient test causes oscillation

Align poles/zeroes using a first-order average model

The LTC3891 is a CM controller designed to step down 28 V to 5 V/6 A. The compensation network on the ITH pin is inconsistent with the equivalent output capacitance and its total ESR, causing oscillation during transient load testing. The switching frequency measured at the output is 23 kHz instead of the expected 500 kHz.

The two circuits of power stage and compensator are combined to form a linear circuit that simulates the closed-loop behavior of the CM architecture.

Figure 14. Linear circuit emulating a CM regulator with misaligned compensation network

Figure 15. Simulation results of linear model, using amplifier as error amplifier, constants are inconsistent

G1 is a voltage controlled current source. Its value is 6, which means that if the voltage at the positive input of G1 is 1 V, its output will provide 6 A. The frequency response of this circuit shows different slope changes at different rates, with a phase of 25° at the 0 dB crossover frequency. Therefore, there are oscillations in the time domain.

To make the time constants consistent, we first need to know the CEQ, ESREQ and RLOAD of the power stage.

R1 is chosen by the designer; here R1 = 11.5 kΩ is chosen, the same as R3. R1 × C1(z) = CEQ × RLOAD(p). Solve for C1:

Figure 16. After pole/zero adjustment alignment, using amplifier as linear model of EA

CEQ × ESREQ (Z) = R1 × C3 (P), the time constant of the compensator pole is determined by R1 × C3. Solve for C3:

When using this average model, the correct simulation results show a slope of -20 dB/Dec and a phase of 90°. If the results are different, you need to verify the calculation.

One of the disadvantages of using an op amp as an EA is that the bandwidth cannot be predicted correctly. Nonetheless, this method is still very practical and can help verify consistent calculations. The bandwidth can be increased by increasing the R1 resistor value. If R1 increases, the compensator capacitance needs to decrease in the same proportion to keep the time constant consistent. R1 cannot be increased indefinitely because the higher the gain, the lower the phase margin at 0 dB. When the time constants are consistent, the phase will always remain 90°. The calculated values need to be verified using the IC switch model, and then transient response benchmarks need to be performed.

Figure 17. Results after pole/zero adjustment alignment, slope of -20 dB/Dec, high phase value of 90°

Figure 18. Compensation network on ITH pin aligned with output LC filter

Figure 19. Simulation results obtained by keeping the relevant values of the compensation network and LC filter consistent, showing a stable response to load transients.

Replacing the op amp with another voltage-controlled current source simplifies the linear model and improves its accuracy. The LTC3891 data sheet provides transconductance values, gm = 2 mmho at 1.2 V. The G1 positive input is 1 V, so the new current value will be 7.2, since 7.2 A/1.2 V = 6 A/V. A simulation of the new circuit (Figure 20) is shown in Figure 21 and the predicted bandwidth will be 46 kHz.

Figure 20. A simpler alignment circuit using G2 as the error amplifier. Its corresponding gm value is taken from the data sheet.

LTpowerCAD predicts a bandwidth of 57 kHz and a phase margin of 52°. The gain plots look very similar. The phase is very close at first but cannot be predicted correctly after 10 kHz.

Right half plane zero (RHPZ)

The RHPZ zero adds 20 dB of gain and reduces the phase by approximately 90°, making it impossible to compensate. For topologies such as boost, buck-boost, and sepic operating in continuous conduction mode, this zero will limit the bandwidth. The frequency position of RHPZ is calculated as follows:

Figure 21. A simpler circuit model using G2 as EA provides wider bandwidth

Figure 22. LTpowerCAD results for the LTC3891 design in Figure 18

Typically, in these equations, "inductance" is the only variable that requires trade-offs by the designer. The RHPZ location limits the bandwidth of the design because the loop needs to close at a frequency of F(RHPZ)/10. The linear model circuit presented here does not take RHPZ into account.

Voltage Mode Buck-Boost Example

The LTC3533 is a VM architecture buck-boost regulator. In boost mode, its RHPZ will be the limiting factor. The LTC3533 demo board is configured for 3.3 V/1.5 A when the input is VIN(MIN) of 2.4 V. In this case, the duty cycle D will be D = (Vo – VIN)/ Vo = (3.3 – 2.4)/3.3 ≈ 0.27. RLOAD = VOUT/IOUT = 3.3/1.5 = 2.2 Ω.

The RHPZ position can be found by any of the following formulas:

The safe position for a closed loop would be at 8.4 kHz. Rt sets the switching frequency Fsw = 1 MHz. Note that due to the lack of RFF, this compensation is type 3-like, so Cff does not create additional high frequency poles.

The positions of the poles and zeros are:

fP[CFF/RFF] → not used (31)

The double pole position of the LC filter is at 15.65 kHz. The two zeros Fz1 and FzCff are clustered together at about 9 kHz to cancel the poles of the LC filter. Additionally, the effect of the zero created by the LC filter at 967 kHz is canceled by the pole at 896 kHz.

Figure 23. LTC3533 demonstration board schematic

Figure 24. First-order model of EA’s VM architecture using op amps; LTC3533 demo board values

Figure 25. Simpler circuit for VM control using a voltage-controlled voltage source

Figure 26. Simulation results of two circuits

An average LTspice circuit using an op amp as EA's VM architecture can be used to check the alignment of poles and zeros. The circuit can be further simplified by using a voltage-controlled voltage source as the EA. Its gain value is derived from the error amplifier AVOL specified in the data sheet, which is 80 dB. 80dB = 20log10000. Therefore, 10000 was used in the simulation. Simulation of both circuits provides very similar solutions. The bandwidth does not vary as in CM circuit simulation. Gains are very similar and phase predictions are 90°, but that just goes to show that correct alignment is possible. The output has an additional 188 μF capacitor and a 0.2 Ω resistor. As shown in Figure 4, voltage-mode LC filters can produce high Q, especially when the values of ESR and DCR are low. To ensure that the LC filter has appropriate damping, an additional RC needs to be added to the output. The specific calculation is as follows:

**Conclusion**

LTspice circuit simulation provides an efficient and reliable method for verifying the calculation of the compensation network. Although the linear model discussed does not include current sensing components, signal gain or RHPZ information, designers will benefit from the fast simulation speed and compatibility with various DC-DC topologies. Furthermore, if the results obtained are correct, the output will show a gain slope of -20 dB/Dec and a phase of approximately 90°.

**References**

1.Henry J. Zhang. "Modeling and Loop Compensation Design of Switch-Mode Power Supplies."

2. "LTspice Simulation Files for Power Stages and Average Compensation Models." Analog Devices, Inc.