CTSD Precision ADC — Part 2: Introducing the CTSD Architecture for Signal Chain Designers
This article will introduce continuous-time sigma-delta (CTSD) ADC technology in a different way than the traditional approach, so that signal chain designers can understand this new and easy-to-use precision ADC technology and think of it as a connection between some of the existing A simple system that knows its components. In Part 1, we highlighted key challenges in existing signal chain designs that can be significantly simplified by utilizing precision CTSD ADCs to achieve high accuracy while maintaining continuous-time signal integrity. The question now is what is behind the CTSD architecture that enables it to achieve these advantages?
The traditional approach to explaining CTSD technology concepts is to first understand the basic principles of the discrete-time sigma-delta (DTSD) modulator loop and then replace the discrete-time loop components with equivalent continuous-time components. While this approach provides insight into Σ-Δ functionality, our goal is to gain a more intuitive understanding of the reasons behind the inherent advantages of precision CTSD ADCs. First, we will outline a step-by-step approach to building a CTSD modulator loop, starting with a common closed-loop inverting amplifier configuration and then combining it with an ADC and DAC. Finally, we will evaluate the basic Σ-Δ functionality of the constructed circuit.
Step 1: Review Closed Loop Inverting Amplifier Configuration
A key advantage of the CTSD ADC is that it provides an easy-to-drive continuous resistive input rather than a traditional front-facing switched capacitor sampler. The inverting amplifier circuit has a similar input impedance concept, which we use as a starting block for building the CTSD modulator loop.
Closed-loop op amp configurations have been the preferred method for replicating analog inputs with high fidelity, and Figure 1 shows one of the common op amp configurations, called the inverting amplifier configuration. 1 One measure of fidelity is the ratio of output to input gain, expressed in Σ-Δ terminology and also known as the signal transfer function (STF). Determining the parameters that affect STF requires circuit analysis.
Figure 1. Closed-loop op amp using inverting amplifier configuration
To consolidate our mathematical knowledge, let's review the origin of the famous VOUT ⁄VIN. First, we assume that the open-loop gain of op amp A is infinite. Based on this assumption, the negative input Vn of the op amp will be at ground potential. Apply Kirchhoff's laws here
Mapping this to VOUT and VIN, we get the gain or STF as
Next, we abandon the unrealistic infinite gain assumption and re-derive the STF under the finite gain A of the operational amplifier, then the STF is as follows:
Here, textbooks usually describe the sensitivity of each parameter RIN, Rf and A. In this example, we continue building the CTSD loop.
Step 2: Introducing Discrete Components into the Amplifier
Our ADC signal chain requires a digital version of VIN. Next, we're going to introduce digital components to this circuit. Instead of placing a sampling ADC directly at the input signal in the traditional way, we tried other methods and placed a typical ADC device after the amplifier output to obtain digital signal data. However, the output of the ADC cannot be used directly as feedback because it must be an analog voltage. Therefore, we need to place a voltage digital-to-analog converter (DAC) after the ADC, as shown in Figure 2.
Figure 2. Introducing ADC and DAC in an inverting amplifier configuration
After using ADC and DAC, VOUT can still represent VIN, but due to the addition of digital components, there is a quantization error. So, there is no change in the signal flow from VIN to VOUT. One thing to note here is that in order to keep the loop function symmetrical with respect to 0 V and to simplify the mathematical derivation, we choose the reference voltage of the ADC and DAC as follows
Step 3: Introducing the Analog Accumulator – Integrator
Is the closed-loop configuration in Figure 2 stable? Both ADC and DAC are discrete components operating on the sampling clock MCLK. Designing a latency-free ADC or DAC has always been an elusive dream for converter experts. Because these loop elements are sequenced, input sampling is typically done on one clock edge and processing on the other clock edge. Therefore, the combined ADC and DAC output VOUT (the feedback in Figure 2) needs to be delayed by 1 clock cycle before it is available.
Does this feedback delay have any impact on stability? Let's take a look at how the VIN is transmitted. To simplify, let's assume VIN = 1, RIN = 1, Rf = 1, and op amp A has a gain of 100. On the first clock cycle, the input voltage is 1 and the DAC output feedback VOUT or VOUTDAC is 0 and is not available until the next clock edge. When we track the error between the input and output feedback of the amplifier and ADC, we can see that the output keeps growing exponentially, which is technically known as the runaway problem.
This is because of the effect the ADC input has on the instantaneous error obtained by the amplifier; that is, even before feedback is obtained, it is certain that the ADC will have this effect, which we do not want. If the ADC affects the accumulated average error data so that the error due to 1 clock cycle delayed feedback reaches the average value, the output of the system will be limited.
The integrator is the analog equivalent of the averaging accumulator. The loop gain is still high, but only high at low frequencies, or in the target frequency bandwidth. This ensures that the ADC does not suffer any transient errors that could lead to a runaway condition. Therefore, the amplifier in the loop is now changed to an integrator followed by an ADC and DAC, as shown in Figure 3a.
Step 4: Simplify the Feedback Resistor
The target component here is DOUTADC. Let’s rearrange the loop components, focusing on using DOUTADC as the output of the system, as shown in Figure 3b. Next, let's consider the simplification of the DAC and Rf paths. To do this, let’s take a closer look at the DAC. The function of the DAC is to convert the DIN digital signal into an equivalent analog current or voltage that is proportional to the reference voltage. To further extend the benefits of reference continuity, we consider a universal DAC architecture based on a resistor ladder that has no switching load on the reference. Let's look at the RTD DAC, 2 which converts DIN to DAC current according to Equation 5.
Where VREF = VREFP – VREFM, which is the total reference voltage of the DAC.
►DIN = digital input in temperature measurement code
►Rf = feedback resistor; split into each unit component
►N = number of digits
Figure 3. (a) Introducing the integrator into the loop. (b) Re-layout the loop, focusing on DOUTADC as the output
Figure 4. Universal temperature measuring resistor DAC
To obtain a voltage output, an op amp in a transimpedance configuration is used for I to V conversion, 3 as shown in Figure 4. therefore,
Returning to the discrete loop of Figure 3b, this VOUTDAC is again converted back to current Ifb through the feedback resistor of the inverting amplifier, that is, the signal flow is IDAC → VOUTDA C → Ifb. Expressed mathematically as:
As can be seen from the signal flow and formula above, converting VOUTDAC to Ifb is a redundant step and can be bypassed. Removing the redundant elements and, for simplicity, denoting (VREFP – VREFM) as VREF, let us redraw the loop as shown in Figure 5.
Figure 5. Remove redundant I-to-V conversion section and feedback resistor.
Look! We constructed a first-order Σ-Δ loop! Connect together all the known components i.e. inverting amplifier, ADC and DAC.
Step 5: Understand Oversampling
So far we have mastered the construction of CTSD loops, but we have not yet realized what is unique about this particular loop. First let’s understand oversampling. ADC data is only useful if there are enough sampled and digitized data points to extract or interpret the analog signal information. The Nyquist criterion recommends that in order to faithfully reconstruct the input signal, the ADC's sampling frequency should be at least twice the signal frequency. If we continue to add more data points based on this minimum requirement, the interpretation error will be further reduced. Following this idea, the sampling frequency chosen in Σ-Δ is much higher than the recommended Nyquist frequency, which is called oversampling. Oversampling 4 spreads the total noise to a higher frequency range, helping to reduce quantization noise in the frequency band of interest, as shown in Figure 6.
Figure 6. Noise spectral density comparison between Nyquist sampling and oversampling
Step 6: Understand Noise Shaping
Signal chain designers should not feel confused when Σ-Δ experts use terms such as noise transfer function (NTF) or noise shaping. 4 Our next step will help them visualize these terms specific to Σ-Δ converters. Let's review a simple inverting amplifier configuration and the resulting error Qe at the amplifier output, as shown in Figure 7.
Figure 7. Error generated in inverting amplifier configuration
The contribution factor of this error at the output can be quantified as
It can be seen from the mathematical formula that the error Qe is attenuated by the open-loop gain of the amplifier, which again demonstrates the advantages of closed-loop.
This understanding of the advantages of closed loop can be extended to the quantization error Qe of the ADC in the CTSD loop, which is caused by the digitization of the continuous signal at the output of the integrator, as shown in Figure 8.
Figure 8. Quantization error Qe generated in the ∑-Δ loop
We can now intuitively conclude that this Qe can be attenuated by the integrator. The integrator TF is |HINTEG (f)|= 1/|s × RC| = 1/2πfRC, and its corresponding frequency domain representation is shown in Figure 9. Its curve is equivalent to the curve of a low-pass filter with high gain at low frequencies, and the gain decreases linearly with increasing frequency. Accordingly, the attenuation change of Qe is similar to the behavior of a high-pass filter.
The mathematical representation of this attenuation factor is the noise transfer function. Let's ignore the sampler in the ADC and the switches in the DAC for now. NTF, VOUTADC ⁄ Qe, can be evaluated in the same way as the inverting amplifier configuration, and its variation curve in the frequency domain is similar to the high-pass filter curve, as shown in Figure 10.
In the target frequency band, the quantization noise is completely attenuated and pushed to high frequencies that are "unrelevant to us". This is called noise shaping.
Figure 10. Noise transfer function without sampler - with high-pass filter curve
Since there is a sampler in the loop, the quantization noise shaping analogy remains unchanged. The difference is that the NTF frequency response will replicate the image at every multiple of fS, as shown in Figure 10, resulting in notches at every integer multiple of the sampling frequency.
Figure 11. Noise transfer function of CTSD ADC
The uniqueness of the Σ-Δ architecture is that it places an integrator and a DAC loop around a raw ADC (e.g., 4-bit ADC), dramatically reducing quantization noise in the frequency bandwidth of interest through oversampling and noise shaping. Turn this raw ADC into a 16-bit or 24-bit precision ADC.
The basic principles of these first-order CTSD ADCs can now be extended to arbitrary-order modulator loops. Sampling frequency, raw ADC specifications, and loop order are the primary design decisions driven by ADC performance requirements.
Figure 9. Integrator transfer function
Step 7: Complete the CTSD Modulator with Digital Filters
Generally speaking, in the ADC signal chain, the digitized data is post-processed by an external digital controller to extract any signal information. We now know that in a Σ-Δ architecture, the signal will be oversampled. If this oversampled digital data were provided directly to an external controller, a large amount of redundant data would need to be processed. This results in excessive power and board space cost overhead in digital controller designs. Therefore, the data should be effectively downsampled without affecting performance before the data is provided to the digital controller. This process is called decimation and is accomplished by a digital decimation filter. Figure 11 shows a typical CTSD modulator with on-chip digital decimation filters.
Figure 12. (a) Block diagram of the CTSD ADC modulator loop from analog input to digital output. (b) Spectral representation of the input signal at the output of the modulator and the output of the digital filter.
Figure 12b shows the frequency response of the in-band analog input signal. At the output of the modulator, we see that noise shaping of the quantization noise results in a significant reduction in the quantization noise in the frequency band of interest. The digital filter helps to attenuate the shaped noise beyond this target frequency bandwidth so that the final digital output DOUT will be at the Nyquist sample rate.
Step 8: Understand the Clock Sensitivity of the CTSD ADC
Now that we know how the CTSD ADC maintains the continuous integrity of the input signal, this greatly simplifies the design of the signal chain. This architecture also has some limitations, mainly dealing with the sampling clock MCLK. The CTSD modulator loop works by accumulating the error current between IIN and IDAC. Any error in this integrated value will cause the ADC in the loop to sample this error and reflect it in the output. For our first-order integrator loop, the integrated value during the Ts sampling period of constant IIN and IDAC is expressed as
For a 0 input, parameters that affect this integration error include
►MCLK frequency: As shown in Equation 10, if the MCLK frequency is scaled, the RC coefficient controlling the integration slope also needs to be rescaled to get the same integration value. This means that the CTSD modulator is tuned for a fixed MCLK clock frequency and cannot support varying MCLK.
►MCLK jitter: DAC code as well as IDAC will change every clock period Ts. If the IDAC time period changes randomly, the average integrated value will keep changing, as shown in Figure 13. Therefore, any error in the form of jitter in the sampling clock period affects the performance of the modulator loop.
Figure 13. Clock sensitivity of CTSD modulator
For the reasons mentioned above, the CTSD ADC is sensitive to the frequency and jitter of MCLK. 5 However, Analog Devices has found ways to address these error issues. For example, the challenge of generating accurate low-jitter MCLK and delivering it to the ADC in the system can be solved by using a low-cost local crystal oscillator close to the ADC. Error issues around fixed sampling frequencies have been addressed through the use of innovative Asynchronous Sample Rate Conversion (ASRC), which does not require fixed sampling MCLK to account for independently variable digital output data rates to the digital controller. Further articles in this series will detail more about this.
Step 9: Voila! Everything is ready to explain the concept of CTSD to your friends!
Part 1 highlighted some of the signal chain advantages of CTSD ADCs, while Part 2 focused on insights into building a modulator loop using closed-loop op amp configuration concepts from steps 1 to 6. Figure 11a also helps us see these advantages.
The input impedance of the CTSD ADC is equivalent to that of an inverting amplifier, which is resistive and easy to drive. Through the use of innovative technology, the reference voltage used by the DAC of the modulator loop is also made resistive. The ADC's sampler is placed after the integrator rather than directly at the input, allowing for inherent aliasing suppression of interference sources outside the frequency band of interest. Continued in this series Over the next few articles, we will delve into these advantages and their impact on the signal chain. In the next article, we'll start with the most unique benefit: inherent aliasing suppression. Stay tuned to Part 3 for details on inherent aliasing suppression and its quantification using a new set of measurement and performance parameters, first introduced with the AD4134 based on the CTSD architecture.
Acknowledgments
The authors would like to thank Praveen Varma and Roberto Maurino for their helpful insights in explaining CTSD ADC technology in a simplified manner.
References
1Hank Zumbahlen. “Micro Tutorial MT-213: Inverting Amplifier.” Analog Devices, February 2013.
2Walt Kester. "MT-014 Tutorial: Basic DAC Architecture I: DAC String and Thermometer (Fully Decoded) DAC." Analog Devices, Inc., 2009.
3Luis Orozco. “Programmable gain transimpedance amplifier maximizes dynamic range of spectroscopy systems.” Analog Dialogue, Volume 47, Issue 2, May 2013.
4Walt Kester. "MT-022 Tutorial: ADC Architecture III: Sigma-Delta ADC Basics." Analog Devices, Inc., 2009.
5Pawel Czapor. “Σ-Δ ADC Clocks—Not Just Jitter.” Analog Dialogue, Volume 53, Issue 3, April 2019.
Pavan, Shanthi, Richard Schreier, and Gabor C. Temes. Understanding the Σ-Δ Data Converter, 2nd Edition. Wiley, January 2017.
Trail:
CTSD Precision ADC - Part 3: Achieving Intrinsic Aliasing Rejection
In the third part of the series of articles on CTSD precision ADC, we will focus on the alias-free characteristics of CTSD ADC, which can improve the anti-interference capability without adding any peripheral design. Part 1 demonstrates a new, easy-to-use, alias-free precision ADC based on the continuous-time Σ-Δ DAC (CTSD) architecture, providing a simple, compact signal chain solution. Part 2 introduces CTSD technology to signal chain designers. This article compares the design complexity behind aliasing suppression solutions for existing precision ADC architectures. We will describe a theory that illustrates the inherent aliasing suppression performance of the CTSD ADC architecture. We also show how to simplify signal chain design and explore the scaling benefits of CTSD ADCs. Finally, we will introduce new measurement and performance parameters to quantify aliasing suppression.
In many applications such as sonar arrays, accelerometers, and vibration analysis, signals outside the bandwidth of the target signal will be detected. These signals are called interference sources. A key challenge for signal chain designers is that ADC sampling causes these interferers to alias into the target signal bandwidth (in-band), causing performance degradation. In addition, in applications such as sonar, in-band aliased interference sources may be misinterpreted as input signals, leading to misidentification of objects around the sonar. The aliasing suppression solution is one of the reasons why the traditional ADC signal chain design is extremely complex. The CTSD ADC itself has aliasing suppression characteristics, and this unique feature brings a new simplified solution. Before we explore this groundbreaking solution, let’s first understand the concept of aliasing.
Step 4: Complete the STF using a digital filter
In order to reduce redundant high-frequency information, the CTSD modulator is used in conjunction with the on-chip digital decimation filter. The combined aliasing suppression TF is shown in Figure 10. Aliasing near fs is attenuated using the inherent aliasing suppression characteristics of CTSD, and intermediate interference sources are attenuated by the digital filter.
Figure 4 compares the AAF order required to achieve –80 dB aliasing rejection for SAR ADCs, DTSD ADCs, and CTSD ADCs at sampling frequency and input signal bandwidth. When using SAR ADC, the order of AFF is the highest, so the complexity is also the highest. CTSD ADC does not need to use an external AAF because its design itself has aliasing suppression performance.
The data sheet for the AD4134, a precision ADC based on the CTSD ADC architecture, introduces a new functional check for measuring aliasing rejection. The ADC's analog input signal frequency is swept and the impact of each out-of-band input signal is calculated by measuring the folded amplitude (if any) of the test frequency tone relative to the used tone.
Figure 11 shows the aliasing suppression performance of the AD4134 for out-of-band frequencies when the performance bandwidth is 160 kHz and the sampling frequency is 24 MHz. For a frequency of 23.84 MHz (fs – 160 kHz), the alias rejection is –85 dB, which is the ADC’s alias rejection specification. It can also be seen from the plot that for other intermediate frequencies the aliasing suppression is higher than –100 dB. For more details on the inherent aliasing rejection, as well as options to further improve this rejection performance, see the AD4134 data sheet.
The input impedance of the CTSD ADC is equivalent to that of an inverting amplifier, which is resistive and easy to drive. Through the use of innovative technology, the reference voltage used by the DAC of the modulator loop is also made resistive. The ADC's sampler is placed after the integrator rather than directly at the input, allowing for inherent aliasing suppression of interference sources outside the frequency band of interest. Continued in this series Over the next few articles, we will delve into these advantages and their impact on the signal chain. In the next article, we'll start with the most unique benefit: inherent aliasing suppression. Stay tuned to Part 3 for details on inherent aliasing suppression and its quantification using a new set of measurement and performance parameters, first introduced with the AD4134 based on the CTSD architecture.