CTSD Precision ADC - Part 3: Achieving Intrinsic Aliasing Rejection
In the third part of the series of articles on CTSD precision ADC, we will focus on the alias-free characteristics of CTSD ADC, which can improve the anti-interference capability without adding any peripheral design. Part 1 demonstrates a new, easy-to-use, alias-free precision ADC based on the continuous-time Σ-Δ DAC (CTSD) architecture, providing a simple, compact signal chain solution. Part 2 introduces CTSD technology to signal chain designers. This article compares the design complexity behind aliasing suppression solutions for existing precision ADC architectures. We will describe a theory that illustrates the inherent aliasing suppression performance of the CTSD ADC architecture. We also show how to simplify signal chain design and explore the scaling benefits of CTSD ADCs. Finally, we will introduce new measurement and performance parameters to quantify aliasing suppression.
In many applications such as sonar arrays, accelerometers, and vibration analysis, signals outside the bandwidth of the target signal will be detected. These signals are called interference sources. A key challenge for signal chain designers is that ADC sampling causes these interferers to alias into the target signal bandwidth (in-band), causing performance degradation. In addition, in applications such as sonar, in-band aliased interference sources may be misinterpreted as input signals, leading to misidentification of objects around the sonar. The aliasing suppression solution is one of the reasons why the traditional ADC signal chain design is extremely complex. The CTSD ADC itself has aliasing suppression characteristics, and this unique feature brings a new simplified solution. Before we explore this groundbreaking solution, let’s first understand the concept of aliasing.
Review of the Nyquist Sampling Criteria
To understand the concept of aliasing, let’s quickly review the Nyquist sampling criterion. We can analyze signals in the time domain or frequency domain. In the time domain, the sampling of an analog signal can be expressed mathematically as a signal multiplication operation, for example, x(t) represents the pulse sequence δ(t), whose duration is Ts.
Figure 1. Time domain representation of the sampling process
Likewise, in the frequency domain, the sampled output can be expressed using a Fourier series as:
It can be seen from Formula 1 that if the frequency axis is expanded, the image of the input signal will be formed at an integer multiple of each sampling frequency fs.
Figure 2. Representation of X(f) after sampling at different sampling frequencies
Equation 1 shows that at frequency f = n × fs - fIN, where n = 0, ±1, ±2..., the signal content X(f) will appear at the fIN position after sampling, as shown in Figure 2 Similar to the undersampling scenario in , this figure shows the sampling phenomenon under various conditions.
In summary, the Nyquist criterion states that any signal greater than half the sampling frequency will be folded or reflected back to frequencies below fs/2 and may fall within the target frequency band.
Assume that the ADC samples at frequency fs, and there are two out-of-band signal tone/interference sources in the system, namely f1 and f2 at the ADC input end, as shown in Figure 3. According to the Nyquist criterion, we can infer that since the frequency of signal tone f1 is less than fs/2, its frequency remains unchanged after sampling. When the frequency of the signal tone f2 is greater than fs/2, it will produce aliasing in the target frequency band fbw_in and reduce the performance of the ADC in this area, as shown in Figure 3a.
This theory also applies to noise above fs/2, which can also fold and appear within the band, increasing the in-band noise floor and degrading performance.
Existing Aliasing Suppression Solutions
To avoid this performance degradation caused by out-of-band (OOB) tones or noise folding, a simple solution is to use a low-pass filter to attenuate signal content exceeding fs/2 before sampling it via the ADC. , this filter is called an anti-aliasing filter (AAF). Figure 3b shows the transfer function of a simple AAF and the attenuated-aliased signal tone at frequency f2 before in-band folding. The main characteristic parameters of this AAF are the filter order and the –3 dB corner frequency. They are determined by passband flatness, the absolute attenuation required at a specific frequency (such as the sampling frequency), and the required attenuation slope beyond the input bandwidth (also called the transition band). Some common filter architectures include Butterworth, Chebyshev, Bessel, and Sallen-Key, which can be implemented using passive RC and op amps. Filter design tools are available to assist signal chain designers in designing AAFs for a given architecture and requirements.
Let us understand the requirements of anti-aliasing filters with an application example. In submarine systems, sonar sensors emit sound waves and analyze underwater echoes to estimate the location and distance of surrounding objects. The input bandwidth of the sensor is 100 kHz, and the system treats signal tones with amplitude >–85 dB detected at the ADC input as effective echo sources. Therefore, any interference from out-of-band needs to be attenuated by at least –85 dB by the ADC to avoid being detected as input by the sonar system. In the next section, we will build and compare alias suppression solutions for different ADC architectures for these requirements.
In traditional ADC architectures, such as successive approximation register (SAR) and discrete time Σ-Δ (DTSD) ADCs, the sampling circuit is located at the analog input of the ADC, which indicates the need to use AAF before the ADC input, as shown in Figure 3b.
AAF Requirements for SAR/Nyquist Sampling ADCs
The sampling frequency of the SAR ADC is generally set to 2 times or 4 times the analog input frequency (fIN). The AAF of this ADC requires a narrow transition band outside the frequency fIN, which means a high-order filter is required. As can be seen in Figure 4, a SAR ADC with a sampling frequency of approximately 1 MHz requires a fifth-order Butterworth filter to achieve –85 dB rejection at frequencies greater than 100 kHz. For filter implementations, as the order of the filter increases, the number of passives and operational amplifiers required increases. This means that the AAF of the SAR ADC requires a large power consumption and area budget in the signal chain design.
AAF requirements for DTSD ADC
Σ-Δ ADCs are oversampled ADCs where the sampling frequency is much higher than the analog input frequency. The aliasing region to consider in AAF design is fs ± fIN. The transition band of the filter requires from fIN to extremely high fs. Compared with SAR ADC AAF, this transition band is wider, indicating that the required AAF order is also lower. As can be seen from Figure 4, for a DTSD ADC with a sampling frequency of 6 MHz, to obtain –85 dB aliasing suppression at a frequency of about fs – 100 kHz, a second-order AAF is generally required.
In practical applications, interference or noise may exist anywhere within the frequency band, not just near the sampling frequency fs. Any frequency tone below fs/2 (such as the tone at frequency f1 in Figure 3) will not appear in the band and thus will not degrade ADC performance. Although AAF can attenuate the signal tone f1 to a certain extent, it will still exist in the ADC output and is redundant information that the external digital controller must process. Can this signal tone be attenuated further so that it no longer appears in the ADC output? One solution is to use an AAF with a narrow transition band outside frequency fIN, but this increases the complexity of the filter design. Another solution is to use an on-chip digital filter in the Σ-Δ modulator loop.
Figure 4. AAF complexity, ADC architecture and target frequency band
Figure 5. STF of DTSD ADC with AAF on the front end and digital filter on the back end.
Digital filter for Σ-Δ modulator loop
In a Σ-Δ ADC, due to oversampling and noise shaping, the modulator output contains a large amount of redundant information, thus requiring extensive processing by an external digital controller. This redundant information processing can be avoided if the modulator data is averaged, filtered, and provided at a lower output data rate (ODR) (typically 2 × fIN). Decimation filters are used to convert the sampling rate from fs to the desired lower ODR. Regarding the use of digital filters for sample rate conversion, which we will explain in a future article, the key point here is that discrete-time Σ-Δ modulators are often used with on-chip digital filters. The combined signal-to-interference transfer function (TF) of a modulator with an analog filter at the front end and a digital filter at the back end is shown in Figure 5.
In summary, the AAF of the DTSD ADC is designed based on the required attenuation of the signal tone around the aliasing area fs. The signal tone in the non-aliasing area (such as f1) is completely attenuated by the on-chip digital filter.
Back-end digital filters and front-end analog filters
SAR ADCs require AAFs with narrow transition bands, while Σ-Δ ADCs require digital filters with narrow transition bands. Digital filters have low power consumption and are easy to integrate into the chip. Additionally, programming the order, bandwidth, and transition bands of a digital filter is much simpler than with an analog filter.
The advantage of oversampling is that it allows a combination of wide-transition-band analog filters and narrow-transition-band digital filters in the backend to provide a solution with superior power consumption, size, and interference immunity.
After using DTSD ADC, although the AAF requirements are relaxed, it increases the design complexity to meet the settling time requirement after each sample, thereby avoiding signal chain performance degradation. The challenge for signal chain designers is to fine-tune the AAF and find a balance between the need for aliasing suppression and the need for output stability.
The new precision CTSD ADC eliminates the need for front-end analog filter design, simplifying signal chain design.
Inherent aliasing rejection of CTSD ADC
Part 2 of this article series introduces a first-order CTSD modulator built from a closed-loop resistive inverting amplifier, as shown in Figure 6. The CTSD modulator follows the same oversampling and noise shaping concepts as the DTSD modulator equivalent to achieve expected performance, and has resistive inputs instead of switched capacitive inputs. The modulator building block consists of a continuous-time integrator, followed by a quantizer to sample and digitize the integrator output, and a feedback DAC to close the input loop. Any noise at the input of the quantizer is noise shaped by the gain transfer function of the integrator.
Figure 6. (a) Building blocks of the CTSD modulator loop and (b) simplified block diagram for mathematical analysis.
Based on the information in Part 2, a simplified block diagram of the CTSD modulator loop can be drawn using the following mathematical model:
·The integrator transfer function is generally called H(f), also called a loop filter. For a first-order integrator, H(f) = 1/2πRC.
·The function of ADC is sampling and quantization. Therefore, the simplified ADC model used for analysis uses a sampler followed by an additive quantization noise source.
·The DAC is a module that multiplies the input by a constant during the current clock cycle. So, it is a module that has a constant impulse response during the sampling clock period and an impulse response of 0 the rest of the time.
The equivalent block diagrams of these simplified models are shown in Figure 6b and can be widely used for Σ-Δ performance analysis. The transfer function from VIN to VOUT is called the signal TF (STF), and the function from Qe to the output is called the noise TF (NTF).
A reasonable explanation for the inherent aliasing suppression characteristics of the CTSD modulator loop is that sampling does not occur directly at the input of the modulator, but occurs after the loop filter H(f), as shown in Figure 6a. To understand the overall picture, the concept will be understood using a linear model without a sampler and the analysis will be extended to cover the loop with a sampler.
Step 1: Implement STF and NTF analysis using linear models
After omitting the sampler to simplify the analysis, the linear pattern should look like Figure 7. The STF and NTF of this loop can be expressed as
According to formula 3, STF can be rewritten as
The target frequency bandwidth is low frequency, which can be expressed mathematically as f→0, and high frequency can be expressed as f→∞. The amplitude of STF and NTF (in dB) as a function of frequency is shown in Figure 7.
Figure 7. (a) Linear model used to simplify analysis, (b) STF(f) = H(f) × NTF(f)
Figure 8. (a) Block diagram of a CTSD modulator loop, input = 0 V, (b) NTF of the modulator loop
Figure 9. Modulator loop rearranged to show its inherent aliasing rejection characteristics
The NTF is similar to a high-pass filter, and the STF is similar to a low-pass filter, with a flat 0 dB amplitude in the target frequency band and attenuation at high frequencies comparable to an AAF TF. Mathematically, the signal passes through a low-pass filter configuration H(f) with high gain and then is processed by the NTF loop. Now, after understanding the NTF block diagram, you can drill down further to understand the loop with the sampler.
Step 2: Block Diagram of NTF
When the input VIN is set to 0 V, the modulator loop block diagram can be rearranged as shown in Figure 8a to represent NTF. When a sampler is included in the loop, the NTF response is similar to the linear model, but duplicate images are displayed at multiples of fs, as shown in Figure 8b.
Step 3: Relay out the modulator loop to visualize pre-filtering operation
If the loop filter H(f) and the sampler of the modulator loop are moved to the input and the feedback is shown in Figure 9, the input to output transfer function does not change. The right side of the rearranged block diagram represents NTF.
Similar to the linear model in step 1, in the sampling equivalent system, the input signal passes through the high gain H(f) and then is sampled and processed through the NTF loop. The lateral portion of the signal after passing through the loop filter forms a low-pass filter configuration before sampling. This configuration results in the inherent aliasing rejection of the CTSD modulator. Therefore, the STF of the CTSD modulator loop is shown in Figure 9.
Step 4: Complete the STF using a digital filter
In order to reduce redundant high-frequency information, the CTSD modulator is used in conjunction with the on-chip digital decimation filter. The combined aliasing suppression TF is shown in Figure 10. Aliasing near fs is attenuated using the inherent aliasing suppression characteristics of CTSD, and intermediate interference sources are attenuated by the digital filter.
Figure 4 compares the AAF order required to achieve –80 dB aliasing rejection for SAR ADCs, DTSD ADCs, and CTSD ADCs at sampling frequency and input signal bandwidth. When using SAR ADC, the order of AFF is the highest, so the complexity is also the highest. CTSD ADC does not need to use an external AAF because its design itself has aliasing suppression performance.
Leveraging CTSD Architecture to Realize Signal Chain Advantages
In some multi-channel applications such as sonar beamforming and vibration analysis, phase information between channels is very important. For example, the phase between channels needs to be precisely matched to an accuracy of 0.05° at 20 kHz.
For the traditional ADC signal chain, passive RC and operational amplifiers are used in the AAF design. The filter causes a certain amplitude and phase drop in the band as a function of the corner frequency. For the sake of reality To achieve good channel-to-channel phase matching, all channels need to have the same roll-off amplitude, which indicates the need for fine control and matching of the filter corner frequency for each channel. A second-order Butterworth filter designed to achieve –80 dB rejection at 16 MHz (sampling frequency) and 160 kHz f3dB (input bandwidth) may have a phase mismatch of ±0.15° at 20 kHz with an error tolerance May be as low as 1% of the absolute value of RC. The available smaller error tolerance RC passive components are limited and increase the bill of materials (BOM) cost.
Since AAF is not required in the CTSD ADC signal chain, channel-to-channel amplitude and phase matching is naturally achieved within the frequency band of interest. Phase mismatch is limited by the on-chip mismatch of the analog modulator loop design and can be as low as ±0.02° at 20 kHz.
Figure 10. CTSD modulator loop with back-end digital filter
Measure and quantify inherent aliasing suppression
The data sheet for the AD4134, a precision ADC based on the CTSD ADC architecture, introduces a new functional check for measuring aliasing rejection. The ADC's analog input signal frequency is swept and the impact of each out-of-band input signal is calculated by measuring the folded amplitude (if any) of the test frequency tone relative to the used tone.
Figure 11 shows the aliasing suppression performance of the AD4134 for out-of-band frequencies when the performance bandwidth is 160 kHz and the sampling frequency is 24 MHz. For a frequency of 23.84 MHz (fs – 160 kHz), the alias rejection is –85 dB, which is the ADC’s alias rejection specification. It can also be seen from the plot that for other intermediate frequencies the aliasing suppression is higher than –100 dB. For more details on the inherent aliasing rejection, as well as options to further improve this rejection performance, see the AD4134 data sheet.
Figure 11. Aliasing suppression versus out-of-band frequencies
The CTSD ADC concepts we illustrate in this article help signal chain designers understand the resistive input, resistive reference, and inherent alias rejection characteristics of this architecture. An easy-to-drive input and reference, as well as the elimination of AAFs in the CTSD ADC signal chain, result in a new, simplified ADC front-end design suitable for a variety of applications. Read the next part of this series to learn more about these simplified precision signal chain designs!
Reference circuit
Anti-aliasing filter design tool
Filter Design Tutorial
Kawle, Abhilasha and Wasim Shaikh. “CTSD Precision ADC — Part 1: How to Improve Precision ADC Signal Chain Design Time.” Analog Dialogue, Volume 55, Issue 1, February 2021.
Kawle, Abhilasha. “CTSD Precision ADC — Part 2: An Introduction to the CTSD Architecture for Signal Chain Designers.” Analog Dialogue, Volume 55, Issue 1, March 2021.
Kester, Walt. “MT-002: What the Nyquist Criterion means for data sampling system design.” Analog Devices, Inc., 2009.
Acknowledgments
The author would like to express his sincere gratitude to Sanjay Kuna, Chip Evaluation Engineer, and Richard Escoto, Senior Test Development Engineer, for their efforts in testing and validating the inherent aliasing suppression.
Trail:
CTSD Precision ADC—Part 4: Easily Drive ADC Inputs and References to Simplify Signal Chain Design
This article focuses on one of the most important architectural features of the new continuous-time Sigma-Delta (CTSD) precision ADC: the ease of driving resistive inputs and voltage references. The key to achieving optimal signal chain performance is to ensure that the input source or reference itself is not destroyed when interfacing with the ADC. When using a traditional ADC, complex signal conditioning circuit design is required to achieve a seamless interface between the input and reference voltage sources and the ADC - called front-end design. The unique architectural features of the CTSD ADC simplify and innovate the interface of this ADC to input and reference voltage sources. First, let’s quickly review the front-end design of a traditional ADC.
In this article, "sensor" and "input signal" are used interchangeably to represent any type of voltage input to the ADC signal chain. The input signal to the ADC signal chain can be a sensor, a signal from some source, or feedback from a control loop. It is well known that in traditional discrete-time Sigma-Delta (DTSD) ADCs and successive approximation register (SAR) ADCs, the sampling network at the input and reference voltage source is a switched capacitive load. When the switch is on, the capacitor charges the input; when the switch is off, the capacitor holds the sampled value. On each sampling clock edge, when the switch reconnects the capacitor to the input, a finite current (called the kickback current) is required to charge or discharge the capacitor to the new sampled value. The curve of this current is shown in Figure 1a. Most sensor and reference ICs are unable to drive kickback currents of this magnitude, and there is a high chance that the input signal or reference will be corrupted if interfaced directly with the ADC. One of the known solutions to avoid this destruction is to use a driver buffer amplifier to isolate the input sensor and reference voltage source from the ADC. The driver amplifier should have the ability to absorb this kickback current, as shown in Figure 1b. This results in the need for high slew rate and high bandwidth amplifiers to support the required input charge/discharge currents and allow the kickback to settle within one sampling time period. These stringent requirements limit the selection of buffer amplifiers that can be used in the input and reference paths of a conventional ADC.