CTSD Precision ADC—Part 4: Easily Drive ADC Inputs and References to Simplify Signal Chain Design
This article focuses on one of the most important architectural features of the new continuous-time Sigma-Delta (CTSD) precision ADC: the ease of driving resistive inputs and voltage references. The key to achieving optimal signal chain performance is to ensure that the input source or reference itself is not destroyed when interfacing with the ADC. When using a traditional ADC, complex signal conditioning circuit design is required to achieve a seamless interface between the input and reference voltage sources and the ADC - called front-end design. The unique architectural features of the CTSD ADC simplify and innovate the interface of this ADC to input and reference voltage sources. First, let’s quickly review the front-end design of a traditional ADC.
Front-end design of traditional ADC
In this article, "sensor" and "input signal" are used interchangeably to represent any type of voltage input to the ADC signal chain. The input signal to the ADC signal chain can be a sensor, a signal from some source, or feedback from a control loop. It is well known that in traditional discrete-time Sigma-Delta (DTSD) ADCs and successive approximation register (SAR) ADCs, the sampling network at the input and reference voltage source is a switched capacitive load. When the switch is on, the capacitor charges the input; when the switch is off, the capacitor holds the sampled value. On each sampling clock edge, when the switch reconnects the capacitor to the input, a finite current (called the kickback current) is required to charge or discharge the capacitor to the new sampled value. The curve of this current is shown in Figure 1a. Most sensor and reference ICs are unable to drive kickback currents of this magnitude, and there is a high chance that the input signal or reference will be corrupted if interfaced directly with the ADC. One of the known solutions to avoid this destruction is to use a driver buffer amplifier to isolate the input sensor and reference voltage source from the ADC. The driver amplifier should have the ability to absorb this kickback current, as shown in Figure 1b. This results in the need for high slew rate and high bandwidth amplifiers to support the required input charge/discharge currents and allow the kickback to settle within one sampling time period. These stringent requirements limit the selection of buffer amplifiers that can be used in the input and reference paths of a conventional ADC.
Figure 1. (a) Kickback current on input and reference of conventional ADC, (b) Kickback current isolated from input and reference by buffer
On the other hand, a low-pass anti-aliasing filter is required at the input to ensure that high-frequency noise and interfering signals are significantly attenuated so that performance does not degrade when they are folded back due to sampling of the frequency band of interest. The challenge facing today's ADC signal chain designers is to fine-tune the competing requirements of aliasing rejection and output stability. The front-end design of the DTSD ADC using the driver and anti-aliasing filter is shown in Figure 2.
The input path consists of an instrumentation amplifier (in-amp), which interfaces the sensor to a fully differential amplifier (FDA), which ultimately drives the ADC. The instrumentation amplifier isolates the input sensor environment from the ADC circuitry. For example, a sensor's common-mode (CM) signal can be very high (up to tens of volts), but most FDAs and ADCs do not support such high input common-mode voltages. Typical instrumentation amplifiers have the ability to support a wide input common-mode voltage while providing an output common-mode voltage suitable for FDA and ADC. Another advantage of instrumentation amplifiers is their high input impedance. This means that if the sensor cannot drive the FDA's input resistor directly, the sensor can interface with the FDA through an instrumentation amplifier. The FDA itself needs to have high bandwidth and high slew rate to allow the output to settle faster. An active anti-aliasing filter (AAF) needs to be built around the FDA to suppress interfering signals.
There are conflicting requirements for drivers of input or reference voltage sources: on the one hand, fast settling requires high bandwidth, but on the other hand, filtering of noise and interference signals requires low bandwidth. On the reference path, the front-end design of the DTSD ADC signal chain is shown in Figure 2. The reference IC is connected to a buffer, which drives the reference load of the ADC. There is also a noise filter in the design to cut off noise from the reference IC and buffer beyond a certain frequency. The design requirements for this filter are discussed later. The reference buffer has high bandwidth and high slew rate requirements to smooth out sample event glitches more quickly.
Part 1 of this article series showed that a new signal chain using a precision CTSD ADC can be 68% smaller than the complex signal chain of a traditional ADC. This size reduction reduces BOM, and the simple design helps signal chain designers get products to market faster.
CTSD ADC Advantages: Positive Input and Reference Voltage Source
Part 2 explains to signal chain designers the CTSD ADC architecture, which takes an unconventional approach to inverting a closed-loop amplifier. As mentioned in Part 2, the CTSD ADC can be thought of as a Sigma-Delta ADC with a resistive input and a reference load. The input and reference structures are simple resistive loads, which means there are no high bandwidth or high slew rate drive requirements. Part 3 demonstrates the unique advantages of CTSD with its inherent aliasing suppression capability to resist interference. In traditional signal chain designs, external alias suppression filters are required to attenuate interfering signals, which is an additional challenge, but the CTSD ADC does not require an external AAF. Due to the inherent aliasing rejection characteristics of the CTSD ADC, the signal transfer function of the modulator loop is equal to the transfer function of the anti-aliasing filter that attenuates high-frequency interference. Due to the resistive input and inherent AAF, the input network is simplified and the sensor can be connected directly to the ADC. In situations where the sensor does not have the capability to drive such a resistive load, an instrumentation amplifier can be used to interface the sensor to the ADC. Similarly, on the reference side, a reference buffer is not required in the CTSD ADC signal chain due to the resistive loading. Figure 3b shows a simplified schematic using an instrumentation amplifier.
Figure 2. Front-end design of discrete-time Sigma-Delta ADC
Figure 3. (a) CTSD architecture provides resistive input and reference load, (b) direct instrumentation amplifier and reference drive CTSD ADC
Figure 4. (a) Kickback in input current of DTSD ADC, (b) Continuous input current curve of CTSD ADC
Figure 4 shows further support for how CTSD ADCs can help simplify input front-end design. For DTSD ADCs, the discontinuity in the input current caused by kickback can be clearly seen when the input sampling switch changes state. For the CTSD ADC, it can be observed that the input current is continuous, which maintains signal continuity.
Simplify input-driven design
We have shown that the input drive of the CTSD ADC is resistive. This section explains how to determine the value of the input impedance RIN when planning the input drive of the ADC. RIN is a function of the ADC's rated noise performance. For example, the AD4134 is a precision CTSD ADC with 108 dB dynamic range, a 4 V reference, and an input impedance of 6 kΩ differential. This shows that when a full-scale 8 V p-p differential input signal is applied, the peak current requirement is 1.3 mA p-p. If the sensor can support input current VIN/RIN, it can interface directly with the ADC. The scenarios that require a simple amplifier to drive such a resistive load are:
1. The sensor does not have the required driving capability to provide the peak current of VIN/RIN.
2. The signal chain design requires gain or attenuation for the sensor output.
3. Isolate the input sensor environment from the ADC circuit.
4. The sensor has a large output impedance.
5. The sensor is located far away from the ADC, and the track wiring may add considerable resistance to the input.
In scenarios 4 and 5, there will be a voltage drop across the additional external resistor RS, which represents a signal loss at the ADC input. This causes gain errors in the signal chain and errors drift with temperature, causing performance degradation. Temperature drift in gain is caused by the different temperature coefficients of the external and internal resistors. This problem can be solved by using a simple amplifier to isolate the additional external resistor. Since the load driven by this amplifier is resistive, the selection criteria for this amplifier are:
·Input impedance: To avoid signal attenuation or loss, the sensor's impedance should match the amplifier input impedance.
·Output impedance: The output impedance should be sufficient to drive the resistive input load of the ADC.
Output type: As a general signal chain design guideline, it is recommended to use a differential signaling strategy for optimal signal chain performance. Differential output type amplifiers or single-ended to differential output design techniques are best suited for this task. Also, for best performance, it is best to set the common mode of this differential signal to VREF/2.
Programmable gain: The input signal is typically amplified or attenuated to map it to the full-scale range of the ADC. This is because the highest performance can be obtained from the ADC signal chain when using the ADC's full-scale input range.
Depending on the application, the amplifier can be an instrumentation amplifier or FDA, or it can be a combination of two single-ended op amps - forming a differential output amplifier. There are no hard requirements for high slew rate or high bandwidth, and one from Analog Devices' broad portfolio of amplifiers can be selected to drive this CTSD ADC based on application needs. In addition, amplifier performance parameters are generally specified with resistive loads, which makes selection simpler.
For example, for the AD4134, a performance-compatible instrumentation amplifier choice with programmable gain options and fully differential outputs is the LTC6373. This instrumentation amplifier provides a high impedance to the input source and can easily drive differential 6 kΩ impedances with noise and linearity performance comparable to ADCs. Through its broad input common-mode support and programmable gain options, any sensor or input signal with a wide range of signal amplitudes can be interfaced with the ADC. An example of an input front-end design using this direct instrumentation amplifier driver is shown in Figure 4.
Figure 5. Input front-end design, direct interface between CTSD ADC and instrumentation amplifier
Another example is a simple low-voltage front-end design using a fully differential driver amplifier such as the LTC6363-0.5/LTC6363-1/LTC6363-2, based on the desired gain or attenuation, as shown in Figure 6. Scenarios where FDA can be used are when the sensor has the capability to drive a resistive load of FDA, but is of the single-ended type or has a common mode that is not supported by the ADC, or the signal chain requires small gain/attenuation.
Figure 6. Input front-end design, direct interface between CTSD ADC and fully differential amplifier
Another example is a low BOM solution that uses two single-ended op amps to convert the single-ended input into a fully differential signal for the ADC, as shown in Figure 7.
Figure 7. Input front-end design, CTSD ADC uses two single-ended amplifiers
There are many other examples of using a combination of a single-ended instrumentation amplifier and a single-ended op amp to build a differential output front end to support very high input common mode or low drive strength single-ended type sensors. Any such combination can be selected to better suit the application based on performance, area and BOM requirements.
Other amplifiers compatible with the AD4134 are:
·Operation amplifiers ADA4625-2, ADA4610-2, AD8605 and ADA4075-2.
·Fully differential amplifiers: ADA4940-2, LTC6363 and ADA4945-1.
·Instrumentation amplifier: AD8421.
The ADI Amplifier Selection Guide can be used to select the amplifier best suited for a specific application. For example, for high linearity applications such as audio test equipment, the ADA4945-1 is recommended. For photodiode applications where very high input impedance is the most important consideration, a transimpedance amplifier (TIA) such as the ADA4610-2 can be used.
The CTSD ADC greatly simplifies the input front end, let's look at similar simplifications in reference driving.
Simplifying reference design
The ADC output is a representation of its input and reference voltage source, as shown in Equation 1.
Where, VIN = input voltage level, VREFADC = ADC reference voltage, N = number of bits, DOUT = ADC digital output.
Equation 1 illustrates the importance of a clean and intact reference voltage source for optimal ADC performance. ADC has the following three main performance indicators that will be affected by the reference voltage error:
Signal-to-noise ratio (SNR): The main noise contributors to SNR are the input path, the ADC itself, and the reference voltage source. For the target total noise at the ADC output, the reference noise budget is typically 1/3 or 1/4 of the standalone ADC output noise, taking into account other noise sources. References or reference buffers typically have higher noise than ADCs. In the data sheet of a reference or reference buffer IC, you can see that spectral noise density or Noisedensity is one of the technical specifications. To review the basics of noise calculations, the total noise at the output of a reference or reference buffer is given by:
We have no control over Noisedensity because it is fixed for the selected reference or buffer. The only controllable parameter is the noise bandwidth (NBW). To reduce reference noise, we need to reduce the noise bandwidth of the reference or reference buffer. This is typically accomplished by connecting a first-order low-pass RC filter to the ADC, as shown in Figure 8. For a first-order RC filter, NBW is given by:
·The ADC reference current IADC flowing through the filter resistor R causes a voltage drop, which changes the actual reference voltage value of the ADC. Therefore, it is recommended to choose a smaller R value and a larger C value to meet the NBW requirement for low reference noise.
Gain Error: As can be seen from Equation 1, VREFADC determines the slope of the output-to-input transfer function, just like in a straight-line equation like y = mx. This slope is also known as the gain of the ADC. Therefore, if the reference voltage source changes, the gain of the ADC will also change.
Linearity: For traditional DTSD ADCs and SAR ADCs, the reference current and accompanying kickback are dependent on the input signal. Therefore, if the reference is not fully settled before the next sample clock edge, the error on the reference will be input-dependent and cause nonlinearity. Mathematically, VREFADC can be expressed as
Referring to Equation 1, based on the input of the ADC, the ADC output DOUT will have various high-order dependencies, which will cause harmonics and integral nonlinearity. Therefore, traditional ADCs strictly require the reference buffer to have a high slew rate and bandwidth to allow the reference output to settle during the sampling time period.
If we analyze SNR and linearity carefully, we see that a voltage reference or a voltage reference buffer has conflicting requirements to meet. Low noise requires low bandwidth, but fast settling requires high bandwidth. Properly balancing these two requirements has been a perennial challenge for signal chain designers. Some latest DTSD ADCs and SAR ADCs integrate reference buffers on-chip to simplify one step in the signal chain design, but these solutions require additional power or compromise performance to some extent. The CTSD ADC does not require a fast settling buffer, nor does its resistive input require a fast settling driver, thus avoiding performance issues.
CTSD ADCs address reference driver challenges with the following features and design improvements:
·The reference voltage source is a resistive load and has no settling requirements on each sampling clock edge. Therefore, designers can connect the reference IC directly to the ADC without the need for a dedicated reference buffer.
·Patented design technology makes the reference current independent of the input and forces the ADC's reference current IADC to remain essentially constant. This is beneficial when an RC filter may be needed to reduce reference noise, as shown in Figure 8. The result is a constant voltage drop across the resistor, with no input-dependent terms added to VREFADC. We designed a measure that digitally corrects the system-level gain error based on the value of R and the voltage measured on the reference pin. Therefore, this simple reference interface will have no gain or linearity errors.
Figure 8. Resistive reference load supports direct connection of reference IC to passive filter
Although measures have been taken to digitally correct the error caused by the voltage drop across R, one may ask whether this will limit the full-scale range of the CTSD ADC, since the actual reference voltage of the ADC (VREFADC) will be smaller than the applied VREF .
For example, if the VREF of the reference IC is adjusted and set to 4.096 V, and the ADC reference current (IADC) = 6 mA, then, for a filter resistor of R = 20Ω, the actual reference voltage of the ADC (VREFADC) is 3.967 V, As shown in Equation 5. In this case, is it possible to saturate the ADC output when a nominal full-scale differential input of 2×VREF = 8.192 V p-p (which is greater than 2×VREFADC) is applied to the ADC input? The answer is "no". The CTSD ADC is designed to support input amplitudes several mV beyond the reference voltage at the ADC pin REFIN. In our AD4134 example, this extended range limits the resistor value to a maximum of 25Ω. The value of C for the noise filter is then chosen to satisfy the calculated noise bandwidth.
Simplifying reference driver design
The CTSD ADC simplifies the design of a reference driver, but there are still other factors to consider when selecting the correct R for the filter and then performing digital gain error correction for the voltage drop across the resistor. Digital gain error correction (also called calibration) is a common feature of many ADCs and allows the signal chain designer to freely compensate for errors in the signal chain at the digital output of the ADC. Therefore, it may not require additional design steps but rather reuse the same algorithm, which is common for many signal chains. In this case, resistor selection may not seem like a special design step, but there is one thing to note: the temperature dependence of the voltage drop. The external filter resistor drifts differently with temperature than the IADC, causing the gain of the VREFADC and ADC to drift with temperature. For applications with strict gain drift requirements, an original solution is to periodically calibrate the signal chain. However, better and more innovative solutions are possible with CTSD technology. Since the ADC reference load current remains constant and is related to the resistive material used on-chip, an on-chip 20Ω filter resistor R can be provided, as shown in Figure 9.
Figure 9. On-chip reference noise filter resistor simplifies reference front-end design for CTSD ADC
In the new front-end design, the reference voltage source IC is connected to the REFIN pin, and the filter capacitor is connected to the REFCAP pin to form a noise filter for the reference voltage source IC noise. Since the resistance of the on-chip resistor R and IADC are both functions of the same resistive material, there is no temperature drift (VREFADC) on REFCAP. The AD4134 also uses a patented on-chip voltage reference correction algorithm to digitally self-calibrate the voltage drop across the on-chip resistor. Therefore, the reference driver design is simplified and only the reference IC and capacitor value need to be selected according to the performance requirements.
The ADR444 is one of the low-noise voltage reference ICs that can be used as a companion device to the CTSD ADC. The AD4134 data sheet provides further details regarding capacitor value selection and internal/external digital gain calibration.
in conclusion
CTSD ADCS removes many barriers to achieving optimal precision performance and simplifies front-end design. In the following article, we will describe how to process the output of the CTSD ADC modulator core into the final digital output format for use by an external digital controller for optimal processing. From the basics of Sigma-Delta introduced in this series of articles, we know that the modulator output cannot be processed directly because it is sampled at a much higher rate. The sampling rate needs to be reduced to the output data rate (ODR) required by the application. Next, we introduce a novel asynchronous sample rate conversion (ASRC) technology that allows the signal chain designer to adjust the final ADC output to any ODR desired, subject to the age-old limitation that ODR can only be a few times the sampling frequency Cease to exist. Stay tuned for these interesting insights!
Reference circuit
“Driving Precision Converters: Selecting a Reference and Amplifier.” Analog Devices.
Mahaffey, Anna. "Driving a SAR ADC (Part 1): Analog Input Model". ADI Corporation.
Shah, Anshul. “Why Does Reference Voltage Noise Matter?” Analog Dialogue, Volume 54, Issue 1, March 2020.